module top_module(
    input clk,
    input areset,  // async active-high reset to zero
    input load,
    input ena,
    input [3:0] data,
    output reg [3:0] q); 

    always @ (posedge clk or posedge areset)
        begin
            if(areset)
                q <= 4'b0;
            else if (load)
                q <= data;
            else if (ena)
                begin
                    q[3:0] <= {1'b0, q[3:1]};
                    //q[3]q[2]q[1]q[0] -->  0q[3]q[2]q[1]，q[0]在移动后消失了，原先q[3]的位置变为0
                end
        end

    // Asynchronous reset: Notice the sensitivity list.
	// The shift register has four modes:
	//   reset
	//   load
	//   enable shift
	//   idle -- preserve q (i.e., DFFs)
	// always @(posedge clk, posedge areset) begin
	// 	if (areset)		// reset
	// 		q <= 0;
	// 	else if (load)	// load
	// 		q <= data;
	// 	else if (ena)	// shift is enabled
	// 		q <= q[3:1];	// Use vector part select to express a shift.
	// end

endmodule
